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SiliconFlow shows why AI tokens are a metered resource

16 min read 3,623 words 36krifanrwoshipm
Token counter draining into a memory chip
A token counter draining into a memory chip.Illustration: generated for this article

Tencent's Token quota turned AI from a background workplace perk into a metered line item: in the second week of June, one employee's previous monthly allowance of $2000 became 1400 yuan and was gone in two days. Woshipm reported that, after the adjustment, different Tencent departments sat on very different monthly Token ceilings, from 1000 yuan for outsourced employees at Tencent Entertainment to about 7000 yuan for employees on the Hunyuan large model team.

That is the pattern this piece follows: AI access exists, but the usable amount is being priced, rationed, and watched.

Doubao shows the same shift on the consumer side. Woshipm said its professional version launched paid continuous monthly subscriptions in the third week of June, with tiers of 68 yuan, 200 yuan, and 500 yuan. A poll two months before that launch had 91,000 participants, of whom 88,000 opposed charging fees. The tension is simple: users want abundant intelligence, while providers pay for tokens moving through scarce compute and memory.

Token quotas make AI spending visible

A token quota turns an AI model from a shared workplace tool into a budget line. According to woshipm, a Tencent employee in the second week of June found that a previous monthly Token quota of $2000 had been changed to 1400 yuan, and the new quota was gone in two days. After the adjustment, different departments had monthly quotas ranging from 1000 yuan to 7000 yuan. The Hunyuan large model team sat near 7000 yuan, while outsourced staff at Tencent Entertainment had only 1000 yuan.

June sequence showing AI usage turning into metered cloud cost
  1. In the second week of JuneTencent employee finds Token quota changed from $2000 to 1400 yuan
  2. In the third week of JuneDoubao launches paid subscriptions for its professional version
  3. On the last day of JuneSiliconFlow submits a prospectus to the Hong Kong Stock Exchange

That is the practical shift: access is no longer the whole question. Workload is.

Doubao shows the same move on the consumer side. In the third week of June, it launched paid subscriptions for the professional version, with continuous monthly tiers of 68 yuan, 200 yuan, and 500 yuan, while repeatedly saying basic functions would remain permanently free. Woshipm also recorded the resistance before pricing arrived: a poll two months earlier had 91,000 participants, and 88,000 opposed charging fees. Free access may preserve habit, but heavier use now has a visible meter attached.

SiliconFlow explains why that meter appears. The company submitted a prospectus to the Hong Kong Stock Exchange on the last day of June. It does not build large models or applications; it schedules chips from Nvidia, Huawei Ascend, and Biren so models including DeepSeek and Qwen can be sold to developers and enterprises by Token volume.

The economics were harsh. SiliconFlow reported 2025 revenue of 55.33 million yuan, up 653% year on year, but its net loss was 345 million yuan, more than 6 times revenue. Gross margin fell from 39.4% in 2024 to -24% in 2025. Its public cloud MaaS business generated 29.26 million yuan, accounting for 52.9% of total revenue, yet had a gross margin of -119%.

Growth did not solve the unit cost problem. Paying customers rose from 2454 to 716,000, an increase of 289 times, while computing power leasing costs were nearly 60 million yuan and accounted for 87% of sales costs. SiliconFlow also issued more than 54 million yuan in vouchers to free users, booked as sales expenses rather than revenue. For small teams, that is the lesson: a model call is not just availability. It is a metered claim on someone's compute bill.

Infrastructure winners do not settle user prices

SiliconFlow sits where AI demand turns into a bill. According to woshipm, it does not build large models or finished applications; it uses its own engine to schedule chips from Nvidia, Huawei Ascend, and Biren, then sells access to models such as DeepSeek and Qwen by token volume. That makes it a useful middle layer to examine, because its accounts show what happens after the infrastructure boom reaches a metered product.

The upstream numbers look very different. Woshipm lists Nvidia's gross margin at 75%, with a Blackwell B200 costing about $6,400 to make and selling for $30,000 to $40,000. TSMC's gross margin is 66%, and its CoWoS capacity is set to move from 35,000 wafers per month at the end of 2024 to 128,000 wafers per month by the end of 2026. Arista has stayed between 62% and 64% for years. ASML's position is even narrower: it is the only company able to produce EUV lithography machines, after twenty years and more than 20 billion euros in research and development.

That margin stack does not automatically become application profit.

SiliconFlow's prospectus showed a net loss of 345 million yuan, more than 6 times revenue. Its gross margin fell from 39.4% in 2024 to -24% in 2025, while its public cloud MaaS business had a gross margin of -119%. Computing power leasing costs were nearly 60 million yuan in 2025, or 87% of sales costs. The company also issued more than 54 million yuan in vouchers to free users, booked as sales expenses without generating revenue.

The contradiction is the point. More than $1 trillion is flowing into AI infrastructure by woshipm's broader count, yet the token seller can still subsidize usage, absorb hardware rental costs, and lose money on cloud MaaS. Local deployment looks cleaner: SiliconFlow generated 26.07 million yuan there in 2025 at an 82.5% gross margin. Public token pricing, then, is not a simple readout of inference cost. It can contain subsidy, customer acquisition, upstream rent, or future lock-in.

The memory wall moved into consumer buying

The old consumer spec sheet taught buyers to look for peak compute. Local inference makes that habit incomplete. According to ifanr, memory capacity determines how large a model a computer can hold, while memory bandwidth determines how quickly data reaches compute cores each second. That distinction matters most during Decode, the autoregressive stage where each new token requires the compute unit to read billions or tens of billions of parameter weights from memory.

TOPS can sit idle if the weights arrive late.

This is why Apple's new Mac positioning reads differently in the agent era. ifanr said Apple's recently released Mac products included a Mac mini framed as a productivity tool for running agents around the clock, while the professional Mac Studio was offered with up to 512GB of unified memory. The standard M6 had 170GB/s of unified memory bandwidth; the M5 Pro reached 307GB/s; the top-end M5 Ultra reached 1.2TB/s. These are buying variables, not just engineering trivia.

Apple also made clustering part of the consumer-adjacent story. ifanr reported that the M5 Pro Mac mini had 3 Thunderbolt 5 ports and supported connecting multiple devices directly into a cluster. On Mac Studio, a distributed inference cluster made from 4 Mac Studio units over Thunderbolt 5, with up to 120Gb/s and RDMA, could reach nearly 3 times the token output throughput of a single machine. The point is practical: when one box cannot feed enough data fast enough, buyers are pushed toward more memory, faster links, or more boxes.

Xiaomi and Nvidia point to the same wall from other angles. Xiaomi's Xuanjie O100, announced one day before the new Mac Studio release, used Wafer-on-Wafer stacking with DRAM wafers above the NPU compute wafer and reached 1.22TB/s of bandwidth, according to ifanr. 36kr said Xuanjie O100 integrates a 14-core NPU, can reach up to 330 Token/s, and ran Xiaomi's built-in MIMO large model offline in a prototype. Nvidia's RTX 5090 took the graphics-card route: 32GB of GDDR7 video memory, a 512-bit bus, and bandwidth close to 1.8TB/s.

SiliconFlow home page with platform links and product overview
SiliconFlow's home page shows its AI model access and developer platform.Screenshot: siliconflow.cn

The memory wall is not new. William A. Wulf and Sally A. McKee published "Hitting the Memory Wall" in 1995, arguing that processor performance was growing much faster than memory bandwidth. ifanr's author applies that old problem to AI: chip performance now depends on compute power and on whether data can be delivered fast enough.

Where AI's data bottleneck shows up across devices, infrastructure, and cloud services

Apple Mac and M-series devicesXiaomi Xuanjie chipsNvidia and AI server stackCloud AI services
Primary constraint describedMemory capacity determines what model a computer can hold; memory bandwidth determines how quickly data reaches compute cores.On-device AI near-memory computing architecture; self-developed chips focus on on-device AI inference, not data-center AI training chips.AI demand is pushing HBM, DRAM, optical modules, connectors, power, and server CPUs into tight supply.Token-metered compute turns model usage into a direct operating cost.
Memory bandwidth or movement dataStandard M6: 170GB/s; M5 Pro: 307GB/s; M5 Ultra: 1.2TB/s.Xuanjie O100: 1.22TB/s; Xuanjie O100 uses 3D Wafer On Wafer stacking and Hybrid Bonding.RTX 5090: bandwidth close to 1.8TB/s; used a 512-bit bus with GDDR7 to raise video memory bandwidth to 1.8TB/s.Not covered.
Memory capacity dataMac Studio offered with up to 512GB of unified memory.A single Xuanjie D100 supports up to 160GB of memory capacity and can support local model deployment with more than 200B parameters.RTX 5090 had 32GB of GDDR7 video memory.Not covered.
Scaling approachM5 Pro Mac mini had 3 Thunderbolt 5 ports; 4 Mac Studio units using Thunderbolt 5, up to 120Gb/s, and RDMA could reach nearly 3 times the token output throughput of a single machine.Xuanjie D100 supports multi-chip fusion computing; Xuanjie O100 integrates a 14-core NPU dedicated to large models.An 8-card AI server typically requires 2 high-end CPUs with 32 or more cores; a 16-card supernode server can require 4 high-end CPUs.SiliconFlow schedules chips from Nvidia, Huawei Ascend, and Biren so models including DeepSeek and Qwen can run and be sold by Token volume.
Cost or pricing pressureApple tried to negotiate lower memory component prices with ChangXin Memory Technologies, but ChangXin Memory Technologies refused; quoted prices no lower than Samsung and SK hynix.Pricing not disclosed in sources.HBM3e 12Hi rose from about $80 at the beginning of 2025 to more than $700 in the second quarter of 2026; PCIe 6.0/CXL connectors rose from less than $10 in 2025 to more than $30 in 2026.Tencent monthly Token quotas ranged from 1000 yuan to 7000 yuan after adjustment; Doubao professional version launched tiers of 68 yuan, 200 yuan, and 500 yuan.
Supply-chain pressureTrendForce survey data said AI data center demand for HBM and high-specification server DDR5 led Samsung, SK Hynix, and Micron to shift limited advanced wafer capacity toward enterprise products.Xiaomi's chip supply details not covered.SK Hynix said its HBM capacity for all of 2026 was completely sold out; Samsung, SK Hynix, and Micron shifted 70%-80% of advanced-process DRAM capacity to HBM production.SiliconFlow's computing power leasing costs were nearly 60 million yuan in 2025, accounting for 87% of sales costs.
Business-model stress signalNon-AI consumer memory buyers are pulled into memory price pressure; phones, consoles, game consoles, and other storage-chip products are affected.Xiaomi has invested more than 18 billion yuan in chipmaking over the past five years and prepared a total budget of 50 billion yuan.CoreWeave's 2026 revenue guidance is $12 billion to $13 billion, backlog is $99.4 billion, operating margin is about 6%, capital expenditure is 250% of annual revenue, and debt is $25 billion.SiliconFlow's gross margin fell from 39.4% in 2024 to -24% in 2025; public cloud MaaS gross margin was -119%.

Memory scarcity raises prices beyond AI buyers

Memory inflation no longer stops at the AI server rack. TrendForce survey data, according to ifanr, showed Samsung, SK Hynix, and Micron moving limited advanced wafer capacity toward HBM and high-specification server DDR5 because AI data centers were paying for them. Micron's exit from the Crucial consumer memory business at the end of last year made the same point from another angle: consumer buyers are losing priority to larger strategic customers.

That priority shift feeds ordinary procurement.

Woshipm's author ties the squeeze to server CPUs as well as memory. Intel and AMD are negotiating supply lock-in agreements lasting one year or longer with Chinese data center customers, but those agreements lock volumes rather than prices. TrendForce reported in July 2026 that Intel began adjusting prices for its full server CPU line in March 2026. Intel's 128-core Granite Rapids Xeon 6980P moved from $12460 to $13955, a $1495 increase, and AMD followed in April 2026 with average EPYC increases of 10%-15% across product lines.

The reason is attachment. An 8-card AI server typically needs 2 high-end CPUs with 32 or more cores, while a 16-card supernode can require 4 high-end CPUs, according to woshipm. Each AI GPU also needs 5-6 HBM stacks, and HBM wafer consumption is 3-4 times traditional DRAM. Woshipm says Samsung, SK Hynix, and Micron have shifted 70%-80% of advanced-process DRAM capacity to HBM production; SK Hynix has said its HBM capacity for all of 2026 is already sold out.

The shortage reaches components that non-AI buyers rarely track until delivery dates slip. Woshipm says PCIe 6.0/CXL high-speed connectors rose from less than $10 in 2025 to more than $30 in 2026, while delivery cycles stretched from 8 weeks to 36 weeks. For optical modules, demand for 1.6T units in 2026 is expected to exceed several million units, while effective capacity for the related 200G EML chips is far below demand.

PC makers are already looking for alternates. Nikkei Asia learned, according to ifanr, that HP, Acer, and Asus certified ChangXin Memory Technologies DRAM this year and began small-volume purchases. Digital Daily reported that Apple tried to negotiate lower memory prices with ChangXin, but ChangXin quoted prices no lower than Samsung and SK hynix.

Where the AI bottleneck shows up first

  • You need to run large-model inference locally rather than send every request to a cloud API. Prioritize memory capacity and memory bandwidth over headline compute alone. The sources state that memory capacity determines how large a model a computer can hold, while memory bandwidth determines how quickly data can be fed to compute cores. Examples include Mac Studio configurations with up to 512GB of unified memory, Xiaomi's Xuanjie O100 with 1.22TB/s of memory bandwidth, and Nvidia's RTX 5090 with 32GB of GDDR7 video memory and bandwidth close to 1.8TB/s.
  • You are comparing single-device inference with a small local cluster. A cluster may help if the machines and interconnect are designed for it, but the interconnect becomes part of the performance budget. The sources describe an M5 Pro Mac mini with 3 Thunderbolt 5 ports and say that a 4-unit Mac Studio cluster using Thunderbolt 5, with up to 120Gb/s, plus RDMA technology could reach nearly 3 times the token output throughput of a single machine.
  • You are budgeting for cloud AI usage or internal employee AI quotas. Expect token-metered compute to be actively managed rather than treated as an unlimited utility. In the second week of June, a Tencent employee found that a previous monthly Token quota of $2000 had been changed to 1400 yuan and was used up in two days. After the adjustment, reported Tencent departmental quotas ranged from 1000 yuan to 7000 yuan. Doubao also launched paid professional subscriptions in the third week of June with continuous monthly subscription tiers of 68 yuan, 200 yuan, and 500 yuan, while emphasizing that basic functions would be permanently free.
  • You are planning AI server procurement or any hardware purchase exposed to server memory, HBM, CPUs, optics, or connectors. Do not assume non-GPU components will stay stable just because the GPU quote is known. The sources report that Samsung, SK Hynix, and Micron shifted 70%-80% of advanced-process DRAM capacity to HBM production; SK Hynix stated its HBM capacity for all of 2026 had been completely sold out; DDR5 server memory prices had risen for three consecutive quarters since the fourth quarter of 2025, with a cumulative increase of more than 200%; and PCIe 6.0/CXL high-speed connectors used in AI servers rose from less than $10 in 2025 to more than $30 in 2026.
  • You are choosing between a public cloud MaaS provider and local deployment for enterprise AI workloads. Scrutinize the economics of token resale. SiliconFlow's prospectus showed that it sold model access by Token volume, but its public cloud MaaS business had a gross margin of -119%, while local deployment solutions generated 26.07 million yuan in revenue in 2025 and had a gross margin of 82.5%. That does not prove every cloud model service is uneconomic, but it shows why cloud AI pricing can tighten when compute leasing costs are high.

New memory formats may not cut the bill

The escape route from token cost looks, at first, like architecture. Put memory closer to compute, widen the pipe, stack the dies, and fewer joules are wasted moving model weights around. Apple's Mac Studio shows the consumer-side version of that idea: ifanr reported configurations with up to 512GB of unified memory, while bandwidth ranged from 170GB/s on the standard M6 to 307GB/s on the M5 Pro and 1.2TB/s on the M5 Ultra.

That is a bandwidth answer, not a free-compute answer.

Xiaomi pushes the same logic harder with Xuanjie O100. According to ifanr and 36kr, the chip reaches 1.22TB/s of memory bandwidth by placing two DRAM wafers above the NPU compute wafer through Wafer-on-Wafer stacking. 36kr says the design uses near-memory computing and Hybrid Bonding, with a 14-core NPU dedicated to large models. The direction is clear: instead of treating memory as a distant pool, the package itself becomes part of the AI accelerator.

Samsung's zHBM concept takes that to the obvious endpoint. ifanr says it stacks HBM directly above the processor to cut latency, with Samsung expecting about 8 times HBM5 performance, more than 10 times HBM5 storage density, 3 times higher energy efficiency, and less than half the thermal resistance. But ifanr also notes an industry view that zHBM heat problems may take more than five years to solve. Vertical distance shrinks. Thermal difficulty grows.

Flash is being pulled into the same contest. Samsung presented nearly 30 storage updates in Santa Clara, including V10 BV-NAND, which uses wafer bonding, passes 400 stacked layers, and improves density by 58% over the mass-produced V9 NAND with 286 layers. SK hynix and SanDisk also released the first HBF specification, with Google and Tenstorrent joining the standardization alliance. ifanr says a 512GB HBF module could be stacked at a cost similar to a mainstream 12-layer 36GB HBM module priced at $300-500.

The catch is timing and demand absorption. HBF is not expected to reach commercial use until at least 2028, according to ifanr. HBM4E is expected to cost twice as much as HBM4, while HBM4 itself is described as moving from $2/Gb to $4~5/Gb. Better packaging can move data faster. Larger models and longer contexts can spend the savings just as quickly.

In your own AI budget, watch for the SiliconFlow split that woshipm documented: public cloud MaaS produced 29.26 million yuan in 2025 revenue and 52.9% of total revenue, yet carried a -119% gross margin. Local deployment produced 26.07 million yuan and an 82.5% gross margin. That gap is the work order: separate routine prompts from heavy jobs, price them by token use, and ask when a smaller model or a local setup changes the bill.

Free usage is not free capacity.

The warning signs are also measurable. SiliconFlow's paying customers rose from 2454 to 716,000, while computing power leasing costs were nearly 60 million yuan and 87% of sales costs. Vouchers above 54 million yuan became sales expenses, not revenue. Track the same lines internally: token spend, subsidized usage, leasing cost, memory capacity, and memory bandwidth before treating AI as a default layer.

For readers outside China

  • Availability: The source material is mainly about Chinese-market reporting and globally relevant hardware supply chains. It does not disclose whether Xiaomi's Xuanjie O100, Xuanjie O3, or Xuanjie D100 will be available outside China. Xiaomi stated that its self-developed chips will focus on on-device AI inference and that AI training chips for data centers are a completely different track. The sources also mention Apple Mac products, Nvidia GPUs, SiliconFlow, Doubao, Tencent internal quotas, and component suppliers including Samsung, SK Hynix, Micron, TSMC, ASML, Arista, Lumentum, Coherent, and Sumitomo, but international retail or enterprise availability is not consistently covered.
  • Pricing: Pricing is only partially disclosed in sources. Doubao's professional version launched continuous monthly subscription tiers of 68 yuan, 200 yuan, and 500 yuan, while saying basic functions would be permanently free. Tencent's reported internal monthly Token quotas after adjustment ranged from 1000 yuan to 7000 yuan, with one employee's quota changed from $2000 to 1400 yuan. Hardware and component prices cited include Intel's Xeon 6980P official guide price rising from $12460 to $13955, a Blackwell B200 GPU end-sale price between $30,000 and $40,000, HBM3e 12Hi rising from about $80 at the beginning of 2025 to more than $700 in the second quarter of 2026, and 6-inch indium phosphide substrates rising from about 8000 yuan per wafer at the beginning of 2025 to 25000-28000 yuan in April 2026. Prices for Apple configurations and Xiaomi chip-equipped products are not disclosed in sources.
  • Closest Western equivalents: Apple Mac Studio and Mac mini used as local AI inference or agent-running machines; Nvidia RTX 5090 as a high-bandwidth consumer GPU comparison point; Cloud API or model-as-a-service platforms that sell model access by token volume, comparable in business role to SiliconFlow's MaaS model; Paid AI assistant subscriptions, comparable in broad user-facing role to Doubao's professional subscription tiers
  • Data residency: The sources do not provide formal data-residency, privacy, compliance, or cross-border data-transfer terms for Doubao, Tencent's internal AI quotas, SiliconFlow, Xiaomi's offline prototype, or Apple's local-device workflows. One Xiaomi prototype equipped with Xuanjie O100 and Xuanjie O3 was shown using Xiaomi's built-in MIMO large model in offline mode, but the source material does not cover where user data is stored, whether telemetry is collected, or what enterprise deployment controls are available.

Sources

The evidence: 88 facts from 6 Chinese articles

Each line below was extracted from the article it sits under, in Chinese, before any of this was written. The writing is done from these and never from the source prose - that separation is structural, not a promise. How we work.

36kr小米低调发布三个芯片,不止瞄准AI手机|最前线

  • Xiaomi released three Xuanjie chips on August 24, 2026: the AI flagship SoC Xuanjie O3, the AI acceleration chip Xuanjie O100, and the intelligent driving high-computing AI chip Xuanjie D100.
  • Xiaomi's chip launch lasted 40 minutes, had no online livestream, and Lei Jun did not attend.
  • Xuanjie O3 is the second flagship SoC independently developed and designed by Xiaomi.
  • Xuanjie O3 continues to use a 3nm process, and its total transistor count increased from 19 billion in the previous generation to 24 billion.
  • Xiaomi deployed AI acceleration units in multiple main modules of Xuanjie O3 in addition to the NPU dedicated to AI tasks.
  • Xuanjie O100 uses an on-device AI near-memory computing architecture independently developed and designed by Xiaomi.
  • Xuanjie O100 uses 3D Wafer On Wafer stacking and Hybrid Bonding technology to bond 2 layers of DRAM wafers and 1 layer of NPU computing wafer together at high temperature.
  • Xuanjie O100 has memory bandwidth of 1.22TB/s and integrates a 14-core NPU dedicated to large models.
  • Xuanjie O100 can reach an on-device large model inference speed of up to 330 Token/s.
  • Xiaomi showed a prototype equipped with Xuanjie O100 and Xuanjie O3 that used Xiaomi's built-in MIMO large model in offline mode.
  • Apple launched the new M6 and M5 Ultra on the day after Xiaomi's chip launch.
  • Apple's M6 uses a 2nm process for the first time and targets daily office work, development, creation, and on-device AI tasks.
  • Xuanjie D100 is Xiaomi's self-developed 3nm high-computing intelligent driving AI chip for the automotive business.
  • Xuanjie D100 contains a 20-core CPU and a 16-core high-computing NPU.
  • A single Xuanjie D100 chip supports up to 160GB of memory capacity and can support local model deployment with more than 200B parameters.
  • Xuanjie D100 supports multi-chip fusion computing and can be applied in the automotive field to run intelligent driving algorithms.
  • Xiaomi restarted flagship SoC research and development in 2021 and launched its first chip product, Xuanjie O1, in 2025.
  • Xiaomi stated that its self-developed chips will focus on on-device AI inference and that AI training chips for data centers are a completely different track.

ifanr为什么苹果、小米的 AI 电脑,都在死磕「内存墙」|AI 器物志

  • Apple's recently released new Mac products included a Mac mini that Apple defined as a productivity tool for running agents around the clock.
  • Apple's professional-grade Mac Studio was offered with up to 512GB of unified memory.
  • The standard M6 had unified memory bandwidth of 170GB/s.
  • The M5 Pro version had unified memory bandwidth of 307GB/s.
  • The top-end M5 Ultra had unified memory bandwidth of 1.2TB/s.
  • Apple made a promotional film for the Mac mini in which the small silver square box grew muscular arms.
  • Xiaomi announced the Xuanjie O100 edge AI acceleration chip one day before the new Mac Studio was released.
  • Xiaomi's Xuanjie O100 had memory bandwidth of 1.22TB/s.
  • Nvidia's RTX 5090 consumer flagship graphics card had 32GB of GDDR7 video memory and bandwidth close to 1.8TB/s.
  • TrendForce survey data showed that surging AI data center demand for HBM and high-specification server DDR5 led Samsung, SK Hynix, and Micron to shift limited advanced wafer capacity toward enterprise products.
  • Micron formally announced at the end of last year that it would gradually exit the Crucial consumer memory business and shift supply chain resources toward larger and more profitable strategic customers.
  • The RTX 5090 used a 512-bit bus with GDDR7 to raise video memory bandwidth to 1.8TB/s.
  • Xiaomi's Xuanjie O100 used wafer-level vertical stacking, also called Wafer-on-Wafer, placing two DRAM wafers directly above the NPU compute wafer.
  • The M5 Pro version of the Mac mini was equipped with 3 Thunderbolt 5 ports and supported connecting multiple devices directly into a cluster.
  • On Mac Studio, a distributed inference cluster made from 4 Mac Studio units using Thunderbolt 5, with up to 120Gb/s, and RDMA technology could achieve nearly 3 times the token output throughput of a single machine.
  • William A. Wulf and Sally A. McKee published the paper "Hitting the Memory Wall" in 1995.

ifanr新内存战争

  • South Korean media outlet Digital Daily reported that Apple previously tried to negotiate lower memory component prices with ChangXin Memory Technologies, but ChangXin Memory Technologies refused.
  • ChangXin Memory Technologies quoted Apple prices no lower than those from Samsung and SK hynix.
  • Samsung presented nearly 30 storage technology updates at the Future of Memory and Storage conference in Santa Clara.
  • Samsung's next-generation NAND flash chip V10 BV-NAND uses wafer bonding technology and reaches more than 400 stacked layers.
  • Samsung's mass-produced V9 NAND version has 286 layers.
  • Samsung's V10 BV-NAND increases memory density by 58% and improves I/O performance.
  • Samsung's zHBM concept stacks HBM directly above the processor to reduce latency.
  • Samsung expects zHBM to have about 8 times the performance of HBM5, more than 10 times the storage density of HBM5, 3 times higher energy efficiency, and less than half the thermal resistance.
  • SK hynix and SanDisk jointly released the first technical specification for HBF, or high-bandwidth flash, the day before Samsung's launch event.
  • Google and AI chip company Tenstorrent have joined the HBF standardization alliance.
  • HBF took six months from the signing of the cooperation memorandum to the release of its specification.
  • A mainstream 12-layer 36GB HBM module is priced at $300-500 per unit, while a 512GB HBF module can be stacked at a similar cost.
  • Nikkei Asia learned that HP, Acer, and Asus completed certification processes for ChangXin Memory Technologies DRAM memory this year and began small-volume purchases of ChangXin Memory Technologies memory.

woshipmAI正在制造一场史无前例的全产业链硬件通胀

  • TrendForce reported in July 2026 that Intel began adjusting prices for its full line of server CPU products in March 2026.
  • Intel's 128-core Granite Rapids Xeon 6980P processor had its official guide price raised from $12460 to $13955, an increase of $1495 or about 12%.
  • In the first quarter of 2026, SK Hynix's quarterly operating profit margin reached 72%, Samsung Electronics' semiconductor division operating profit margin reached 73%, and Micron Technology's operating profit margin reached 69%.
  • Nomura Securities' forecast model shows HBM average selling price rising from about $12/GB in 2026 to $24.1/GB in 2027.
  • SK Hynix stated that its HBM capacity for all of 2026 has been completely sold out.
  • In July 2026, Zhongji Innolight stated at an investor exchange meeting that its orders on hand already covered all of 2026 and some orders had been scheduled into 2027.

woshipm一万亿美元砸向 AI,真正赚到钱的只有这三类公司

  • Microsoft, Amazon, Alphabet, and Meta have a combined 2026 capital expenditure upper limit of $725 billion.
  • The combined 2026 capital expenditure upper limit of Microsoft, Amazon, Alphabet, and Meta is 77% higher than in 2025.
  • In July this year, U.S. early-stage technology investor Chris Zeoli analyzed the AI infrastructure industry chain layer by layer and produced statistics on it.
  • A Blackwell B200 GPU has a manufacturing cost of about $6,400.
  • A Blackwell B200 GPU has an end-sale price between $30,000 and $40,000.
  • Nvidia has a gross margin of 75%.
  • CUDA is a programming platform that Nvidia spent more than ten years building.
  • In January 2025, DeepSeek released the V3 model and claimed it completed training for only $5.6 million.
  • Nvidia's share price fell 16.97% on the day when the market reacted to DeepSeek's V3 training-cost news.
  • Nvidia lost $589 billion in market value in a single day after the market reacted to DeepSeek's V3 training-cost news.
  • Eighteen months after Nvidia's market reaction to DeepSeek's V3 training-cost news, Nvidia's market value had risen 8 times from its low and reached $4.85 trillion.
  • TSMC has a gross margin of 66%.
  • TSMC's CoWoS capacity expanded from 35,000 wafers per month at the end of 2024 to 128,000 wafers per month by the end of 2026.
  • ASML is the only company in the world that can produce EUV lithography machines.
  • ASML spent twenty years and invested more than 20 billion euros in research and development for EUV lithography technology.
  • Arista's gross margin has stayed between 62% and 64% for years.
  • A GB200 rack has power consumption of 120 to 140kW, which is 16 to 18 times that of a traditional rack.
  • CoreWeave's 2026 revenue guidance is $12 billion to $13 billion, its backlog is $99.4 billion, its operating margin is about 6%, its capital expenditure is 250% of annual revenue, and it has $25 billion of debt on its balance sheet.

woshipm没人逃得过Token账单

  • In the second week of June, a Tencent employee found that the employee's previous monthly Token quota of $2000 had been changed to 1400 yuan, and the quota was used up in two days.
  • In the third week of June, Doubao officially launched paid subscriptions for its professional version, with continuous monthly subscription tiers of 68 yuan, 200 yuan, and 500 yuan.
  • A poll two months before Doubao's paid subscription launch had 91,000 participants, of whom 88,000 opposed charging fees.
  • Doubao repeatedly emphasized that its basic functions would be permanently free.
  • On the last day of June, SiliconFlow submitted a prospectus to the Hong Kong Stock Exchange.
  • SiliconFlow was founded 35 months before the prospectus submission described in the source.
  • SiliconFlow does not build large models or applications, and instead uses its self-developed engine to schedule chips from vendors including Nvidia, Huawei Ascend, and Biren so models including DeepSeek and Qwen can run and be sold to developers and enterprises by Token volume.
  • SiliconFlow's prospectus showed 2025 revenue of 55.33 million yuan, up 653% year on year.
  • SiliconFlow's prospectus showed a net loss of 345 million yuan, more than 6 times its revenue.
  • SiliconFlow's gross margin fell from 39.4% in 2024 to -24% in 2025.
  • SiliconFlow's public cloud MaaS business had a gross margin of -119%.
  • SiliconFlow's public cloud MaaS service generated 29.26 million yuan in revenue in 2025, accounting for 52.9% of total revenue.
  • SiliconFlow's number of paying customers rose from 2454 to 716,000, an increase of 289 times.
  • SiliconFlow's computing power leasing costs were nearly 60 million yuan in 2025, accounting for 87% of sales costs.
  • SiliconFlow issued more than 54 million yuan in vouchers to free users, and these vouchers were all booked as sales expenses and did not generate revenue.
  • SiliconFlow's research and development expenses were 209 million yuan, equal to 378% of total revenue.
  • SiliconFlow's local deployment solutions generated 26.07 million yuan in revenue in 2025 and had a gross margin of 82.5%.